Designing better PCBs: using minimum clearances wisely

On a recent visit to our factories in Eger I asked the PCB manufacturing manager, József Lengyel, and his team, what are the top ten customer-data issues that they experience. The answer was unanimous and immediate: designers using the tightest design rules on the entire board instead of just to the specific places where they are absolutely required. I then asked what the other nine issues were, to which I got an unexpected response: the same answer!

Design Rules: One Size Does Not Fit All

When we layout a board we usually start by focusing on the hard parts – fine-pitch QFNs, BGAs, strict connector placements, etc. – which will determine the tightest minimum track-widths and clearances that we can get away with, and eventually determine the manufacturing costs. At some point we’ll look at PCB manufacturers’ minimum clearances – track-to-track, pad-to-track, etc. – for our board, and set the EDA tool’s DRC accordingly. These settings will be, most often, applied to the entire board, which means that these minimum clearances will appear throughout the board, even where there’s plenty of space, rather than only where needed.

Now, as designers we assume that this isn’t a problem because we’re paying for those settings for the entire board, so the manufacturer can, and should, just deal with it. It turns out that this is a problem for both the manufacturer and the designer, in the long run.

Why Overusing Minimum Clearances Hurts Everyone

For the manufacturer, there are now many more potential manufacturing fault points throughout the board that they need to identify, check, tweak, and, in some cases, report back as issues to be fixed by the designer, causing delays. Then the reality of manufacturing kicks in: with decreasing clearances the number of defects increase. This ends up affecting manufacturing times and cost, and if we consider the operation as a whole, increases costs for everyone.

For the designer, this amount of difficult spots may be an issue later during a production run: manufacturing three boards is quite a different matter than manufacturing 3,000! Switching to a different manufacturer is another potential pain-point since they might not be able to deal with these issues as well as the previous one, or make different decisions about what to do with minor problems. All this may decrease yield and quality, increase cost, and affect delivery times.

So here’s the tip. Use the smallest DRC settings only where absolutely necessary and relax them everywhere else. Some EDA tools won’t make this straightforward, but there’s usually a way to arm-twist them into being helpful with this. In any case, we should think of minimum clearance spots in the same way that we think of number of layers, component count, or BoM line-items: fewer is better! It will make you a better circuit-board designer, and, as a bonus, manufacturers will love you.

Many thanks to Geert Willems (imec, EDM Forum) for his comments on drafts of this article.

Further reading:

• EDM Forum’s (imec) EDM-D-000, Good Design-for-X Practice, provides many more points for good design-for-manufacturing practices; section 5, specifically 5.6 to 5.10 deals with the topic of this article. (The article is available free after registration.)
• 10 Rules for better data